Cartridge Board

What Is It?

A very complex board made by Nintendo
256K of PRG ROM
8K of WRAM
74HC4040 12 bit binary counter (3)
74HC08 quad 2-in AND gate
74HC74 dual D-type flipflop
74HC30 8-input NAND gate
74CH04 hex inverter

The Tech:

Wow. Here it is. The Nintendo World Championship cartridge. This represents Nintendo's peak. You could compete against others all across the country for big prizes! I remember going to the World of Nintendo when it came through town, and what an experience it was.

Anyways, this board contains ALOT of hardware. Two 128K PRG ROMs, 8K of WRAM, 8K of CHR RAM, an MMC1, a huge string of counters, and some control logic. The dip switches set the time period that the cart gives the player before it expires.

One interesting thing to note, is that the lockout chip's reset line is used on here to initialize some of the hardware... This means the cart WILL NOT WORK on toploading NES units. (or, if it does work it will act very flaky).

Using the hardware:

Dip switch settings...

switch|time (mins)
OOOO - 5.001
OOOC - 5.316
OOCO - 5.629
OOCC - 5.942
OCOO - 6.254
OCOC - 6.567
OCCO - 6.880
OCCC - 7.193
COOO - 7.505
COOC - 7.818
COCO - 8.131
COCC - 8.444
CCOO - 8.756
CCOC - 9.070
CCCO - 9.318
CCCC - 9.695

O = switch open ("off"), C = switch closed ("on")

The cart uses an MMC1, but the connections are quite "funny" to say the least.

There are 2 128K EPROMS.  One is connected up to the MMC1's program
bank switch pins like normal, and when enabled the cart acts like a
regular old MMC1 with 128K of PRG ROM.

The CHR bits of the MMC1 control the second 128K EPROM's address lines.

They use the register at $A000-$BFFF to set these bits.  The register at
$C000-$DFFF is not used.

Bit 0 is not used (which would've been for 4K CHR banks)
Bit 1 and 2 select which 32K PRG bank to use
Bit 3 :

 0 - select the lower 128K which is the CHR-bank controlled ROM
 1 - select the upper 128K which is the PRG-bank controlled ROM

Bit 4 : Initialize cart and start/stop timer

On startup, the first 128K is switched in, and the first 32K of this ROM
is switched in no matter what.  To "clear" this condition, you must write
a 0, then 1 to bit 4 of the CHR bank.  this will clock a flipflop, which
will then release control of bits 1 through 3.

After this initialization,  it has the following properties:

0 - allow timer to run
1 - reset and clear the timer


The timer is a HUGE 30 bit counter, that runs off of M2.  It increments 1 for
every M2 cycle.  When the proper bits are all 1, an IRQ is fired off.

      29          Counter Bits             0
       H4 321x xxxx xxxx xxxx xxxx xxxx xxxx

The "H" bit must be 1 for the counter to fire an interrupt.

Bits 1-4 run through the dipswitch.  When the dipswitch is closed, the bit
is used in the timing.  When the dipswitch is open, it is pulled high by
a resistor and is therefore disabled.

Normally, all of the switches are open.
This gives a time of 5.00362 minutes.

All HTML and graphics designed and copyright by Kevin Horton.