Super Donkey Kong
What Is It?
This is one of those "Pirate Original" single-game cartridges. The game isn't too shabby, even though there's only 6 or so levels.
Your standard running/jumping platformer, with a Donkey Kong Country flair.
Yup, this cart's got 3 glop tops on it. The mapper is really weird and fucked-up, and I barely figured enough
of it out to write a plugin to read it through CopyNES. The code was "mined" with invalid opcodes to slow down reverse-engineering.
Listen to the NSF file!
Here's how the mapper works:
This mapper is very similar to MMC3, so alot of the same material will be skipped. Please
refer to the MMC3 page for info on how it works.
Similar to the MMC3, this accepts writes to 8000,8001, A000,A001, C000,C001, and E000-E003.
It also accepts writes to 6000, 6001, and possibly a couple other locations in this area.
It seems to use A0, A1, A13, A14, and A15 in decoding.
Registers 6001, 6003, 8000, and A001 are implemented (or at least decoded) but don't
appear to do anything. Make sure to mask these off during writes to 8001, A000, and C000
or else problems can occur.
Register 6000 controls the main PRG banking, while CHR is solely controlled through the
M: PRG ROM bank control
0 - the MMC3 portion controls PRG banking
1 - 6000 controls PRG banking
Z: PRG ROM size.
0 - 16K
1 - 32K
Bb: PRG bank bits.
b = bits that are not verified
These bits select a 16K bank when Z = 0, and a 32K bank when Z = 1. When selecting a 32K
bank, bit 0 is not used. Therefore, to select 32K bank #1 you must write A2h to this
This register is obviously for multicart usage. This allows NROM games to be run through
this mapper by simply selecting a desired size and bank. The CHR banks are still operated
through the MMC3 portion no matter what.
This register is quite odd. Writing anything here over-rides all PRG banking settings and
loads the first 32K bank of the ROM into the PRG space. I assume this is to allow a quick
method of selecting a multicart menu. Writing 00h to 6000h puts the MMC3 back in charge.
A000 is the "control" register on this mapper, while C000 is the "data" register.
It works quite similar to the MMC3.
7 bit 0
C: CHR Address Invert. When set, does an effective XOR of 1000h with the CHR addresses.
S: PRG ROM swapping control.
0 - 8000-9FFFh and A000-BFFFh can be swapped out while C000-FFFFh is fixed.
1 - A000-BFFFh and C000-DFFFh can be swapped out while 8000-9FFFh is fixed.
Note: E000-FFFFh is hardwired to the last 8K of the PRG ROM.
S = 0: 8000-9FFFh is hardwired to the second to last 8K bank of the PRG ROM.
S = 1: C000-DFFFh is hardwired to the second to last 8K bank of the PRG ROM.
M: Mode bits
000b 0 - Select 2 1K CHR ROM pages at 0000h in PPU space
001b 1 - Select 1K CHR ROM page at 1400h in PPU space
010b 2 - Select 2 1K CHR ROM pages at 0800h in PPU space
011b 3 - Select 1K CHR ROM page at 1C00h in PPU space
100b 4 - Select 8K PRG ROM page at 8000h or C000h
101b 5 - Select 8K PRG ROM page at A000h
110b 6 - Select 1K CHR ROM page at 1000h in PPU space
111b 7 - Select 1K CHR ROM page at 1800h in PPU space
Note: the modes are ALL re-arranged with respect to the MMC3. Prolly an effort
to foil RE'ing.
Data register for the desired bank#.
7 bit 0
M: Mirroring control
0 - Vertical mirroring
1 - Horizontal mirroring
This mapper does not support WRAM.
Interrupts are sorta similar to the MMC3, so read up on them there.
E000/E002 will reset and disable the IRQ flag.
Note: writing to E000 will set PRG to the first 32K of the PRG ROM! (see above)
E001/E003 will enable the IRQ flag.
C001 is the IRQ counter register. This is direct access to the IRQ counter itself. There
is no buffer register like on the MMC3. Every 8 PPU A12 clocks, this register is decremented.
When it reaches ffh, an IRQ is triggered.
Writing to E002 (to disable/reset the flag) and then to E003 (to re-enable IRQs) will not
reload the counter. It will then trigger in another 256 scanlines unless a new count is
loaded into C001.
Reading this location returns what appears to be 3 jumper/dip switch inputs. Since these
are not pinned on the cart, I cannot confirm. D0-D2 would be the switch inputs if they